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87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 1 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator g eneral d escription the ics87158 is a high performance 1-to-6 lvpecl-to-hcsl/lvcmos clock generator and is a member of the hiperclocks? family of high performance clock solutions from ics. the ics87158 has one differential input (which can accept lvds, lvpecl, lvhstl, sstl, hcsl), six differential hcsl output pairs and two complementary lvcmos/lvttl outputs. the six hcsl output pairs can be individually con- figured for divide-by-1, 2, and 4 or high impedance by use of select pins. the two complementary lvcmos/lvttl outputs can be configured for divide by 2, divide by 4, high imped- ance, or driven low for low power operation. the primary use of the ics87158 is in intel ? e8870 chipsets that use intel ? pentium 4 processors. the ics87158 converts the differential clock from the main system clock into hcsl clocks used by intel ? pentium 4 processors. however, the ics87158 is a highly flexible, general purpose device that operates up to 600mhz and can be used in any situation where differential-to-hcsl translation is required. f eatures ? six hcsl outputs ? two lvcmos/lvttl outputs ? one differential lvpecl clock input pair ? pclk, npclk supports the following input types: lvds, lvpecl, lvhstl, sstl, hcsl ? maximum output frequency: 600mhz (maximum) ? output skew: 100ps (maximum) ? propagation delay: 4ns (maximum) ? 3.3v operating supply ? 0c to 85c ambient operating temperature ? available in both standard and lead-free rohs compliant packages ? industrial temperature information available upon request hiperclocks? ic s b lock d iagram p in a ssignment gnd v dd v dd _r pclk npclk gnd_r v dd _m mref nmref gnd_m v dd gnd v dd _l v dd gnd_l sel_t mult_0 mult_1 v dd _l gnd_l sel_a sel_b sel_u pwr_dwn# v dd gnd_h v dd _h host_p1 host_n1 gnd_h host_p2 host_n2 v dd _h host_p3 host_n3 gnd_h host_p4 host_n4 v dd _h host_p5 host_n5 gnd_h host_p6 host_n6 v dd _h iref gnd_i v dd _i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-lead tssop 6.1mm x 12.5mm x .92mm body package g package top view 48-lead ssop 7.5mm x 15.9mm x 2.3mm body package f package top view v dd host_p1 host_n1 gnd_h v dd host_p6 host_n6 gnd_h v dd host_p2 host_n2 gnd_h v dd host_p3 host_n3 gnd_h v dd host_p4 host_n4 gnd_h v dd host_p5 host_n5 gnd_h v dd mref nmref gnd_h current adjust 1,2,4 mult_0 mult_1 iref pwr_dwn# sel_t pclk npclk sel_a sel_b sel_u divider control - + 1,2,4 2,4
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 2 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 2 1 , 1d n gr e w o p. d n u o r g y l p p u s r e w o p 8 4 , 4 1 , 1 1 , 2v d d r e w o p. s n i p y l p p u s e v i t i s o p 3v d d r _r e w o p . s t u p n i k c o l c e c n e r e f e r l a i t n e r e f f i d r o f n i p y l p p u s r e w o p 4k l c pt u p n i. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 5k l c p nt u p n i. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i 6r _ d n gr e w o p. s t u p n i l a i t n e r e f f i d r o f d n u o r g y l p p u s r e w o p 7v d d m _r e w o p. s t u p t u o k c o l c f e r m r o f n i p y l p p u s r e w o p 9 , 8 , f e r m f e r m n t u p t u o a o t k c o l c e c n e r e f e r a s a d e d i v o r p s k c o l c d e d n e e l g n i s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . r e v i r d k c o l c y r o m e m 0 1m _ d n gr e w o p. s t u p t u o k c o l c f e r m r o f d n u o r g y l p p u s r e w o p 3 1v d d l _r e w o p. s n i p t u p n i c i g o l r o f n i p y l p p u s r e w o p 0 2 , 5 1l _ d n gr e w o p. s n i p t u p n i c i g o l r o f d n u o r g y l p p u s r e w o p 6 1t _ l e st u p n in w o d l l u p . s t u p t u o l l a s e t a t s i r t t u p n i h g i h e v i t c a . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 10 _ t l u mt u p n in w o d l l u p r o t c a f g n i y l p i t l u m e h t s t c e l e s s n i p o w t e s e h t n o g n i t t e s c i g o l e h t . s t u p t u o r i a p t s o h e h t r o f t n e r r u c e c n e r e f e r f e r i e h t f o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 11 _ t l u mt u p n ip u l l u p r o t c a f g n i y l p i t l u m e h t s t c e l e s s n i p o w t e s e h t n o g n i t t e s c i g o l e h t . s t u p t u o r i a p t s o h e h t r o f t n e r r u c e c n e r e f e r f e r i e h t f o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9 1v d d l _r e w o p. s n i p t u p n i c i g o l r o f n i p y l p p u s r e w o p 3 2 , 2 2 , 1 2 , a _ l e s , b _ l e s u _ l e s t u p n in w o d l l u p . s e i c n e u q e r f t u p t u o d e r i s e d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 2# n w d _ r w pt u p n ip u l l u p f e r m s e c r o f l a n g i s n w o d - r e w o p l t t v l w o l - e v i t c a s u o n o r h c n y s a t u p t u o p _ t s o h s e v i r d d n a , s t u p t u o n _ t s o h s e t a t s i r t , w o l s t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . f e r i x 2 o t s t n e r r u c 5 2v d d i _r e w o p. t u p n i e c n e r e f e r t n e r r u c f e r i r o f n i p y l p p u s r e w o p 6 2i _ d n gr e w o p . t u p n i e c n e r e f e r t n e r r u c f e r i r o f d n u o r g y l p p u s r e w o p 7 2f e r it u p n i e c n e r e f e r a s e d i v o r p d n u o r g o t n i p s i h t m o r f r o t s i s e r n o i s i c e r p d e x i f a . s t u p t u o k c o l c t s o h e d o m - t n e r r u c l a i t n e r e f f i d r o f d e s u t n e r r u c 6 4 , 0 4 , 4 3 , 8 2v d d h _r e w o p . s t u p t u o k c o l c t s o h l a i t n e r e f f i d e h t r o f s n i p y l p p u s r e w o p 0 3 , 9 2 , 6 n _ t s o h 6 p _ t s o h t u p t u o. s l e v e l e c a f r e t n i l s c h . s r i a p t u p t u o l a i t n e r e f f i d 7 4 , 3 4 , 7 3 , 1 3h _ d n gr e w o p . s t u p t u o k c o l c t s o h l a i t n e r e f f i d e h t r o f d n u o r g y l p p u s r e w o p 3 3 , 2 3 , 5 n _ t s o h 5 p _ t s o h t u p t u o. s l e v e l e c a f r e t n i l s c h . s r i a p t u p t u o l a i t n e r e f f i d 6 3 , 5 3 , 4 n _ t s o h 4 p _ t s o h t u p t u o. s l e v e l e c a f r e t n i l s c h . s r i a p t u p t u o l a i t n e r e f f i d 9 3 , 8 3 , 3 n _ t s o h 3 p _ t s o h t u p t u o. s l e v e l e c a f r e t n i l s c h . s r i a p t u p t u o l a i t n e r e f f i d 2 4 , 1 4 , 2 n _ t s o h 2 p _ t s o h t u p t u o. s l e v e l e c a f r e t n i l s c h . s r i a p t u p t u o l a i t n e r e f f i d 5 4 , 4 4 , 1 n _ t s o h 1 p _ t s o h t u p t u o. s l e v e l e c a f r e t n i l s c h . s r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d d u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 3 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t able 2. p in c haracteristics t able 3a. c ontrol i nput f unction t able s t u p n is t u p t u o r w p # n w d _ l e s t _ l e s a _ l e s b _ l e s u _ 1 p _ t s h 1 n _ t s h 2 p _ t s h 2 n _ t s h 3 p _ t s h 3 n _ t s h 4 p _ t s h 4 n _ t s h 5 p _ t s h 5 n _ t s h 6 p _ t s h 6 n _ t s h p _ f e r m n _ f e r m 10000 2 2 2 2 2 2 4 10001 z i h2 2 2 2 z i h4 10010 4 2 2 2 2 4 4 10011 4 4 4 4 4 4 4 10100 1 1 1 1 1 1 4 10101 z i h1 1 1 1 z i h4 10110 2 1 1 1 1 2 4 10111 2 2 2 2 2 2 2 11xxx z i hz i hz i hz i hz i hz i hz i h 0xxxx 1 p _ t s h f e r i x 2 = 2 p _ t s h f e r i x 2 = 3 p _ t s h f e r i x 2 = 4 p _ t s h f e r i x 2 = 5 p _ t s h f e r i x 2 = 6 p _ t s h f e r i x 2 = p _ f e r m w o l = 1 n _ t s h z i h = 2 n _ t s h z i h = 3 n _ t s h z i h = 4 n _ t s h z i h = 5 n _ t s h z i h = 6 n _ t s h z i h = n _ f e r m w o l = s t u p n i s n o i t a r u g i f n o c e c i v e d 0 _ t l u m1 _ t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r v = f e r i d d /) r r * 3 ( t n e r r u c t u p t u ov h o 0 5 @ t n e m n o r i v n e 00 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i i h o f e r i * 5 =v 6 . 0 01 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i i h o f e r i * 6 =v 7 . 0 10 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i i h o f e r i * 4 =v 5 . 0 11 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i i h o f e r i * 7 =v 8 . 0 t able 3b. f unction t able l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 4 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t able 4c. d ifferential dc c haracteristics , v dd = 3.3v5%, t a = 0c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n ik l c p n , k l c pv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n ik l c p n , k l c pv d d v , v 5 6 4 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0 + d n gv d d 5 8 . 0 -v . f e r m n o t u o z h m 0 5 d n a x x _ t s o h n o t u o z h m 0 0 1 , n i z h m 0 0 2 t a d e r u s a e m s r e t e m a r a p l l a v r o f t e s t s u j d a t n e r r u c h o . y l n o s t u p t u o x x _ t s o h o t r e f e r s t n e m e r u s a e m . v 7 . 0 = v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n d d . v 3 . 0 + t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v5%, t a = 0c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, t a = 0c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 5 6a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v m v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v m i h i t n e r r u c h g i h t u p n i # n w d _ r w p , 1 _ t l u mv d d v = n i v 5 6 4 . 3 =5a , b _ l e s , a _ l e s , u _ l e s , t _ l e s 0 _ t l u m v d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i # n w d _ r w p , 1 _ t l u mv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a , b _ l e s , a _ l e s u _ l e s , t _ l e s 0 _ t l u m v d d v , v 5 6 4 . 3 = n i v 0 =5 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v . f e r m n o t u o z h m 0 5 d n a x x _ t s o h n o t u o z h m 0 0 1 , n i z h m 0 0 2 t a d e r u s a e m s r e t e m a r a p l l a v r o f t e s t s u j d a t n e r r u c h o . y l n o s t u p t u o x x _ t s o h o t r e f e r s t n e m e r u s a e m . v 7 . 0 = 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t d d , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t m a r a p e e s . 2 / . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 48 lead tssop 58.3c/w (0 lfpm) 48 lead ssop 52.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 5 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t able 5a. hcsl ac c haracteristics , v dd = 3.3v5%, t a = 0c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 6z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 7 . 30 . 4s n t ) o ( k s5 , 4 , 2 e t o n ; w e k s t u p t u o 0 60 0 1s p t ) p p ( k s5 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 5s p t ) c c ( t i jr e t t i j e l c y c - o t - e l c y c 0 5 1s p t r e m i t e s i r t u p t u o% 0 8 o t % 0 25 7 10 0 7s p t f e m i t l l a f t u p t u o% 0 8 o t % 0 25 7 10 0 7s p c d oe l c y c y t u d t u p t u o8 42 5% . f e r m n o t u o z h m 0 5 d n a x x _ t s o h n o t u o z h m 0 0 1 , n i z h m 0 0 2 t a d e r u s a e m s r e t e m a r a p l l a v r o f t e s t s u j d a t n e r r u c h o . y l n o s t u p t u o x x _ t s o h o t r e f e r s t n e m e r u s a e m . v 7 . 0 = . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l 3 + t a d e t a l u c l a c e u l a v m u m i x a m : 4 e t o n . l a c i p y t m o r f . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 5 e t o n t able 4d. hcsl dc c haracteristics , v dd = 3.3v5%, t a = 0c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h o t n e r r u c t u p t u o 9 . 2 19 . 4 1a m v h o e g a t l o v h g i h t u p t u o 5 7 4 = f e r r 0 5 = d a o l r , i h o f e r i * 6 = 7 . 0v v l o e g a t l o v w o l t u p t u o 5 7 4 = f e r r 0 5 = d a o l r , i h o f e r i * 6 = 3 0 . 0v i z o t n e r r u c e g a k a e l e c n a d e p m i h g i h 0 1 -0 1a v x o e g a t l o v r e v o s s o r c t u p t u o 0 8 20 3 4v m . f e r m n o t u o z h m 0 5 d n a x x _ t s o h n o t u o z h m 0 0 1 , n i z h m 0 0 2 t a d e r u s a e m s r e t e m a r a p l l a v r o f t e s t s u j d a t n e r r u c h o . y l n o s t u p t u o x x _ t s o h o t r e f e r s t n e m e r u s a e m . v 7 . 0 = l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 3z h m t ) c c ( t i jr e t t i j e l c y c - o t - e l c y cc l f p 0 3 / f p 0 1 =0 5 1s p t r e m i t e s i r t u p t u o c , v 4 . 2 o t v 4 . 0 l f p 0 1 =4 . 0s n c , v 4 . 2 o t v 4 . 0 l f p 0 3 =8 . 1s n t f e m i t l l a f t u p t u o c , v 4 . 2 o t v 4 . 0 l f p 0 1 =4 . 0s n c , v 4 . 2 o t v 4 . 0 l f p 0 3 =2s n c d oe l c y c y t u d t u p t u oc l f p 0 3 / f p 0 1 =8 42 5% . f e r m n o t u o z h m 0 5 d n a x x _ t s o h n o t u o z h m 0 0 1 , n i z h m 0 0 2 t a d e r u s a e m s r e t e m a r a p l l a v r o f t e s t s u j d a t n e r r u c h o . y l n o s t u p t u o f e r m o t r e f e r s t n e m e r u s a e m . v 7 . 0 = t able 5b. lvcmos / lvttl ac c haracteristics , v dd = 3.3v5%, t a = 0c to 85c
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 6 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator scope 10pf/30pf lvcmos 450 scope qx hcsl p arameter m easurement i nformation d ifferential i nput l evel 3.3v lvcmos o utput l oad ac t est c ircuit 3.3v hcsl o utput l oad ac t est c ircuit 0v o utput s kew hcsl o utput r ise /f all t ime lvcmos o utput r ise /f all t ime 3.3v5% 0v v cmr cross points v pp gnd pclk npclk v dd t sk(o) host_nx clock outputs 20% 80% 80% 20% t r t f v sw i n g 3.3v5% host_px host_ny host_py clock outputs 0.4v 2.4v 2.4v 0.4v t r t f v dd , v dd _x gnd v dd , v dd _x gnd
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 7 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t pd pclk npclk host_px host_nx p ropagation d elay lvcmos o utput d uty c ycle /p ulse w idth /p eriod hcsl o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% host_px host_nx t period t pw t period odc = v ddo 2 x 100% t pw mref, nmref
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 8 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels vdd r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. i nputs : pclk/npclk i nput : for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k resistor can be tied from pclk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos outputs can be left floating. there should be no trace attached. hcsl o utput all unused hcsl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 9 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver ter- mination requirements. f igure 2a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 2b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 2c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 2f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 2e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 2d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 10 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator s chematic e xample figure 3 shows an example of the ics87158 lvpecl to hcsl clock generator schematic. in this example, the ics87158 is configured as follows: pwr_dwn# = 1 mult_[1:0] = 10, rref = 475 , iref = 2.32ma, i oh = 6*iref sel_[a,b,u] = 000, mref = pecl 4, all host output = pecl 2 sel_t = 0, output enable zo = 50 50mhz, lvcmos/lvttl c10 0.1uf c10 0.1uf zo = 50 zo = 50 200mhz, 3.3v lvpecl ics8431-11 (u1-13) r2 50 3.3v lvpecl r8 28 + - r4 50 (u1-19) r9 28 zo = 50 (u1-28) (u1-40) zo = 50 (u1-14) vdd=3.3v (u1-23) r5 50 c10 0.1uf ics9222-01_refclk (u1-34) c5 0.1uf (u1-48) ics9222-01_refclk c6 0.1uf ics8431-01 u1 85158 1 2 3 4 5 6 7 8 9 10 35 36 25 27 28 32 31 29 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 30 33 34 42 41 40 39 38 37 46 45 44 43 47 48 gnd vdd vdd_r pecl npecl gnd_r vdd_m mref nmref gnd_m host_n4 host_p4 vdd_i iref vdd_h host_n5 gnd_h host_n6 vdd gnd vdd_l vdd gnd_l sel_t mult_0 mult_1 vdd_l gnd_l sel_a sel_b sel_u pwr_dwn# gnd_i host_p6 host_p5 vdd_h host_p2 host_n2 vdd_h host_p3 host_n3 gnd_h vdd_h host_p1 host_n1 gnd_h gnd_h vdd c9 0.1uf vdd=3.3v c4 0.1uf zo = 50 100mhz, hcsl rref 475 c3 0.1uf c7 0.1uf (u1-46) c8 0.1uf (u1-11) c10 0.1uf (u1-2) (u1-25) (u1-7) c5 0.1uf r6 33 c9 0.1uf r1 50 vdd=3.3v r7 33 r3 50 f igure 3. ics87158 s chematic l ayout
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 11 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator power and ground this section provides a layout guide related to power, ground and placement of bypass capacitors for a high- speed digital ic. this layout guide is a general recommen- dation. the actual board design will depend on the compo- nent types being used, the board density and cost con- straints. the description assumes that the board has clean power and ground planes. the principle is to minimize the esr between the clean power/ground plane and the ic power/ground pin. a low esr bypass capacitor should be used on each power pin. the value of bypass capacitors ranges from 0.01uf to 0.1uf. the bypass capacitors should be located as close ic c via gnd pin power pin gnd pads power pads f igure 4. r ecommended l ayo u t of b ypass c apacitor p lacement to the power pin as possible. it is preferable to locate the bypass capacitor on the same side as the ic. figure 4 shows suggested capacitor placement. placing the by- pass capacitor on the same side as ic allows the capaci- tor to have direct contact with the ic power pin. this can avoid any vias between the bypass capacitor and the ic power pins. the vias should be place at the power/ground pads. there should be minimum one via per pin. increase the number of vias from the power/ground pads to power/ground planes can improve the conductivity.
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 12 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator d2 b) input with internal pull down resistor d2 input_down d1 d1 input_pu ru 51k vdd rd 51k vdd a) input with internal pull up resistor l ogic c ontrol i nput the logic input control signals are 3.3v lvcmos compatible. the logic control input contains esd diodes and either pull-up or pull-down resistor as shown in figure 5. the data sheet pro- vides pull-up or pull-down information for each input pin. leav- ing the input floating will set the control logic to default setting. hcsl d river t ermination the hcsl is a differential constant current source driver. the output current is set by control pins mult_[1:0] and the value of resistor rref. in the characteristic impedance of 50 ohm environment, the match load 50 ohm resistors r4 and r5 are terminated at the receiving end of the transmission line. the 33 ohm series resis- tor r6 and r7 should be located as close to the driver pins as possible. for the clock traces that required very low skew should have equal length. other general rules of high-speed digital design also should be followed. some check points are listed as follows: - avoid sharp angles on the clock trace. sharp angle turn causes the characteristic impedance change on the transmission lines. - keep the clock trace on same layer. whenever possible, avoid any vias on the middle clock traces. any via on middle the trace can affect the trace characteristic impedance and hence degrade signal quality. - there should be sufficient space between the clock traces that have different frequencies to avoid cross talk. - no other signal trace is routed between the clock trace pair. - transmission line should not be routed across the split plane on the adjacent layer. to set logic high, the input pin connected directly to v dd . to set logic low, the control input connect directly to ground. for con- trol signal source from the driver that has different power sup- ply, a series current resistor of greater than 100 ohm is required for random power on sequence. f igure 5. l ogic i nput c ontrols
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 13 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ics87158 is: 2631 t able 6a. ja vs . a ir f low t able f or 48 l ead tssop p ackage ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 82.6c/w 70.3c/w 63.7c/w multi-layer pcb, jedec standard test boards 58.3c/w 52.3c/w 49.9c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6b. ja vs . a ir f low t able f or 48 l ead ssop p ackage ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 52.9c/w 46.0c/w 42.0c/w
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 14 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator p ackage o utline - g s uffix for 48 l ead tssop t able 6a. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 4 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b7 1 . 07 2 . 0 c9 0 . 00 2 . 0 d0 4 . 2 10 6 . 2 1 ec i s a b 0 1 . 8 1 e0 0 . 60 2 . 6 ec i s a b 0 5 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 p ackage o utline - f s uffix for 48 l ead ssop t able 6b. p ackage d imensions reference document: jedec publication 95, mo-118 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 4 a1 4 . 20 8 . 2 1 a0 2 . 00 4 . 0 b0 2 . 04 3 . 0 c3 1 . 05 2 . 0 d5 7 . 5 10 0 . 6 1 e3 0 . 0 18 6 . 0 1 1 e0 4 . 70 6 . 7 ec i s a b 5 3 6 . 0 h8 3 . 04 6 . 0 l0 5 . 02 0 . 1 0 8
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 15 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t able 7. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the ics logo is a registered trademark, and hipercl ocks is a trademark of integrated circuit systems, inc. all other trademarks are the property of their respective owners and may be registered in certain jurisdictions. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 8 5 1 7 8 s c ig a 8 5 1 7 8 s c ip o s s t d a e l 8 4e b u tc 5 8 o t c 0 t g a 8 5 1 7 8 s c ig a 8 5 1 7 8 s c ip o s s t d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 f l g a 8 5 1 7 8 s c if l g a 8 5 1 7 8 s c ip o s s t " e e r f - d a e l " d a e l 8 4e b u tc 5 8 o t c 0 t f l g a 8 5 1 7 8 s c if l g a 8 5 1 7 8 s c ip o s s t " e e r f - d a e l " d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 f a 8 5 1 7 8 s c if a 8 5 1 7 8 s c ip o s s d a e l 8 4e b u tc 5 8 o t c 0 t f a 8 5 1 7 8 s c if a 8 5 1 7 8 s c ip o s s d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 f l f a 8 5 1 7 8 s c if l f a 8 5 1 7 8 s c ip o s s " e e r f - d a e l " d a e l 8 4e b u tc 5 8 o t c 0 t f l f a 8 5 1 7 8 s c if l f a 8 5 1 7 8 s c ip o s s " e e r f - d a e l " d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
87158ag www.icst.com/products/hiperclocks.html rev. b march 10, 2006 16 integrated circuit systems, inc. ics87158 1- to -6, lvpecl- to -hcsl/lvcmos 1, 2, 4 c lock g enerator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 1 6 8 . 5 d n a 4 n i p r o f r o r r e o p y t d e t c e r r o c - t n e m n g i s s a n i p . m a r g a i d t i u c r i c t s e t d a o l t u p t u o s o m c v l v 3 . 3 d e t c e r r o c . m a r g a i d t u p n i l a i t n e r e f f i d g n i v i r d l a n g i s d e d n e e l g n i s d e t a d p u . t a m r o f d e t a d p u 3 0 / 5 1 / 1 b 2 t a 4 t 3 4 9 c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 i d e g n a h c - e l b a t y l p p u s r e w o p d d . x a m a m 5 6 o t l a c i p y t a m 8 4 . n o i t c e s e c a f r e t n i t u p n i k c o l c l c e p v l d e t a d p u 4 0 / 4 2 / 6 b 7 t 1 5 1 . n o i t c e s s e r u t a e f o t t e l l u b e e r f - d a e l d e d d a . e l b a t n o i t a m r o f n i g n i r e d r o o t r e b m u n t r a p e e r f - d a e l d e d d a 4 0 / 8 / 7 b 7 t 8 5 1 d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . e t o n d n a r e b m u n t r a p e e r f - d a e l p o s s t d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 6 0 / 7 1 / 1 b7 t5 1 d e t c e r r o c d n a , g n i k r a m e e r f - d a e l p o s s t d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o . t n u o c r & t p o s s t 6 0 / 0 1 / 3

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